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? semiconductor components industries, llc, 2014 november, 2014 ? rev. 0 1 publication order number: ncv4299c/d ncv4299c 150 ma low-dropout voltage regulator the ncv4299c is a family of precision micropower voltage regulators with an output current capability of 150 ma. it is available in 5.0 v or 3.3 v output voltage. the output voltage is accurate within 2% with a maximum dropout voltage of 0.5 v at 100 ma. low quiescent current is a feature drawing only 80 a with a 100 a load. this part is ideal for any and all battery operated microprocessor equipment. the device features microprocessor interfaces including an adjustable reset output and adjustable system monitor to provide shutdown early warning. an inhibit function is available. with inhibit active, the regulator turns off and the device consumes less than 1.0 a of quiescent current. the part can withstand load dump transients making it suitable for use in automotive environments. features ? 5.0 v, 3.3 v 2%, 150 ma ? extremely low current consumption ? 80 a (typ) in the on mode ? 1.0 a in the off mode ? early warning ? reset output low down to v q = 1.0 v ? adjustable reset threshold ? wide temperature range ? fault protection ? 60 v peak transient voltage ? ?40 v reverse voltage ? short circuit ? thermal overload ? internally fused leads on so?14 package ? inhibit function with 1 a current consumption in the off mode ? aec?q100 grade 1 qualified and ppap capable ? these are pb?free devices so?14 d2 suffix case 751a pin connections so ro q inh gnd gnd gnd gnd 114 gnd gnd i d si radj marking diagrams x, xx = 3 or 33 (3.3 v version) = 5 or 50 (5.0 v version) a = assembly location wl, l = wafer lot y = year ww, w = work week g or = pb?free package www. onsemi.com 1 14 see detailed ordering and shipping information in the package dimensions section on page 17 of this data sheet. ordering information v4299cxxg awlyww 1 14 (note: microdot may be in either location) soic?14 gnd d 1 8 ro radj so si q i so?8 d1 suffix case 751 1 8 299cx alyw 1 8 soic?8
ncv4299c www. onsemi.com 2 figure 1. so?8 simplified block diagram i bandgap reference + - ? + 1.36 v si radj + - + current limit and saturation sense + - 1.85 v 7.1 a ro so d gnd q r so r ro pin function description ? so?8 package pin symbol description 1 i input. battery supply input voltage. bypass directly to gnd with ceramic capacitor. 2 si sense input. can provide an early warning signal of an impending reset condition when used with so. connect to q if not used. 3 radj reset adjust. use resistor divider to q to adjust reset threshold lower. connect to gnd if not used. 4 d reset delay. connect external capacitor to ground to set delay time. 5 gnd ground. 6 ro reset output. npn collector output with internal 20 k pullup to q. notifies user of out of regulation condition. leave open if not used. 7 so sense output. npn collector output with internal 20 k pullup to q. can be used to provide early warning of an impending reset condition. leave open if not used. 8 q 5.0 v, 3.3 v, 2%, 150 ma output. use 22 f, e s r 4 to ground.
ncv4299c www. onsemi.com 3 figure 2. simplified block diagram i bandgap reference inh + - ? + 1.36 v si radj + - + current limit and saturation sense + - 1.85 v 7.1 a ro so d gnd q r ro r so pin function description pin no. soic?14 symbol description 1 radj reset adjust. use resistor divider to q to adjust reset threshold lower. connect to gnd if not used. 2 d reset delay. connect external capacitor to ground to set delay time. 3 gnd ground 4 gnd ground 5 gnd ground 6 inh inhibit. connect to i if not needed. a high turns the regulator on. use a low pass filter if transients with slew rate in excess of 10 v/ s may be present on this pin during operation. see figure 34 for details. 7 ro reset output. npn collector output with internal 20 k pullup to q. notifies user of out of regulation condition. 8 so sense output. npn collector output with internal 20 k pullup to q. can be used to provide early warning of an impending reset condition. 9 q 5.0 v, 3.3 v, 2%, 150 ma output. use 22 f, e s r 4 to ground. 10 gnd ground 11 gnd ground 12 gnd ground 13 i input. battery supply input voltage. 14 si sense input. can provide an early warning signal of an impending reset condition when used with so.
ncv4299c www. onsemi.com 4 maximum ratings rating symbol min max unit input voltage to regulator (dc) v i ?40 45 v input peak transient voltage to regulator wrt gnd (note 1) ? ? 60 v inhibit (inh ) v inh ?40 45 v sense input (si) v si ?40 45 v sense input (si) i si ?1.0 1.0 ma reset threshold (radj) v radj ?0.3 7.0 v reset threshold (radj) i radj ?10 10 ma reset delay (d) v d ?0.3 7.0 v reset output (ro) v ro ?0.3 7.0 v reset output (ro) i ro ?20 20 ma sense output (so) v so ?0.3 7.0 v output (q) v q ?0.3 16 v output (q) i q ?5.0 ? ma esd capability, human body model (note 3) esd hb 2.0 ? kv esd capability, machine model (note 3) esd mm 200 ? v esd capability, charged device model (note 3) esd cdm 1.0 ? kv junction temperature t j ? 150 c storage temperature t stg ?50 150 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. recommended operating range input voltage 5.0 v version 3.3 v version v i 5.5 4.4 45 45 v junction temperature t j ?40 150 c functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. lead temperature soldering reflow (note 2) reflow (smd styles only), lead free 60 s?150 sec above 217, 40 sec max at peak t sld ? 265 pk c moisture sensitivity level so?8 so?14 msl level 1 level 1 1. load dump test b (with centralized load dump suppression) according to iso16750?2 standard. guaranteed by design. not tested in production. passed class c according to iso16750?1 2. per ipc / jedec j?std?020c. 3. this device series incorporates esd protection and is tested by the following methods: esd hbm tested per aec?q100?002 (js?001?2010) esd mm tested per aec?q100?003 (eia/jesd22?a115) esd cdm tested per aec?q100?011 (eia/jesd22?c101). thermal characteristics characteristic test conditions (typical value) unit note 4 note 5 note 6 thermal characteristics, so?8 junction?to?lead ( jlx , jlx ) junction?to?ambient (r ja , ja ) 72 198 58 150.7 58.3 124.5 c/w thermal characteristics, so?14 junction?to?lead ( jlx , jlx ) junction?to?ambient (r ja , ja ) 15.1 142.7 19.9 101.2 19.3 86.1 c/w thermal characteristics, tssop?14 ep junction?to?tab ( jlx , jlx ) junction?to?ambient (r ja , ja ) 9.7 111.6 11.4 78.7 11.7 53.7 c/w 4. 2 oz copper, 50 mm sq copper area, 1.5 mm thick fr4. 5. 2 oz copper, 150 mm sq copper area, 1.5 mm thick fr4. 6. 2 oz copper, 500 mm sq copper area, 1.5 mm thick fr4.
ncv4299c www. onsemi.com 5 electrical characteristics (?40 c < t j < 150 c; v i = 13.5 v unless otherwise noted.) characteristic symbol test conditions min typ max unit output q output voltage (5.0 v version) v q 1.0 ma < i q < 150 ma, 6.0 v < v i < 16 v 4.9 5.0 5.1 v output voltage (3.3 v version) v q 1.0 ma < i q < 150 ma, 5.5 v < v i < 16 v 3.23 3.3 3.37 v current limit i q v q = 90% of v qnom 250 430 500 ma quiescent current (i q = i i ? i q ) i q inh on, i q < 100 a, t j = 25 c ? 80 90 a quiescent current (i q = i i ? i q ) i q inh on, i q < 100 a, t j 125 c ? 80 95 a quiescent current (i q = i i ? i q ) i q inh on, i q = 10 ma ? 200 500 a quiescent current (i q = i i ? i q ) i q inh on, i q = 50 ma ? 0.8 2.0 ma quiescent current (i q = i i ? i q ) i q inh = 0 v, t j = 25 c ? ? 1.0 a dropout voltage (note 7) v dr i q = 100 ma ? 0.26 0.50 v load regulation v q i q = 1.0 ma to 100 ma ? 1.0 30 mv line regulation v q v i = 6.0 v to 28 v, i q = 1.0 ma ? 2.0 25 mv power supply ripple rejection psrr ?r = 100 hz, vr = 1.0 vpp, i q = 100 ma ? 66 ? db inhibit (inh ) inhibit off voltage v inh off v q < 0.1 v ? ? 0.8 v inhibit on voltage 5.0 v version 3.3 v version v inh on v q > 4.9 v v q > 3.23 v 3.5 3.5 ? ? ? ? v input current i inh on i inh off inh = 5 v inh = 0 v ? ? 3.8 0.01 10 2.0 a reset (ro) switching threshold 5.0 v version 3.3 v version v rt ? 4.50 2.96 4.67 3.07 4.80 3.16 v output resistance r ro ? 10 20 40 k reset output low voltage 5.0 v version 3.3 v version v ro v q = 4.5 v, internal r ro , i ro = ?1.0 ma v q = 2.96 v, internal r ro , i ro = ?1.0 ma ? ? 0.05 0.05 0.40 0.40 v allowable external reset pullup resistor v roext external resistor to q 5.6 ? ? k delay upper threshold v ud ? 1.5 1.85 2.2 v delay lower threshold v ld ? 0.4 0.5 0.6 v product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 7. only for 5 v version. measured when the output voltage v q has dropped 100 mv from the nominal value obtained at v i = 13.5 v.
ncv4299c www. onsemi.com 6 electrical characteristics (continued) (?40 c < t j < 150 c; v i = 13.5 v unless otherwise noted.) characteristic symbol test conditions min typ max unit reset (ro) delay output low voltage 5.0 v version 3.3 v version v d,sat v q = 4.5 v, internal r ro v q = 2.96 v, internal r ro ? ? ? 0.017 0.1 0.1 v delay charge current i d v d = 1.0 v 4.0 7.1 12 a power on reset delay time t d c d = 100 nf 17 28 35 ms reset reaction time t rr c d = 100 nf 0.5 1.6 4.0 s reset adjust switching threshold 5.0 v version 3.3 v version v radj,th v q = 3.5 v v q = 2.3 v 1.26 1.26 1.36 1.36 1.44 1.44 v input voltage sense (si and so) sense input threshold high v si,high ? 1.34 1.45 1.54 v sense input threshold low v si,low ? 1.26 1.36 1.44 v sense input hysteresis ? (sense threshold high) ? (sense threshold low) 50 90 130 mv sense input current i si v si = 1.2 v ?1.0 0.1 1.0 a sense output resistance r so ? 10 20 40 k sense output low voltage v so v si = 1.2 v, v i = 5.5 v, i so = 0 a ? 0.1 0.4 v allowable external sense out pullup resistor r soext ? 5.6 ? ? k si high to so high reaction time t psolh r soext = 5.6 k ? 1.3 8.0 s si low to so low reaction time t psohl r soext = 5.6 k ? 2.2 5.0 s thermal shutdown thermal shutdown temperature (note 8) t sd i out = 1 ma 150 ? 200 c 8. values based on design and/or characterization. ncv4299c i inh d radj si q ro so gnd i i i inh i d c d 100 nf i radj i si v radj v si v inh v i i q v q v ro v so i q figure 3. measurement circuit
ncv4299c www. onsemi.com 7 typical performance characteristics ? 5.0 v option figure 4. output voltage vs. junction temperature figure 5. output voltage vs. input voltage figure 6. charge current vs. junction temperature figure 7. drop voltage vs. output current figure 8. switching voltage vs. junction temperature 5 2 1 0 010 v q , output voltage (v) v i , input voltage (v) 4 3 2 6 14 figure 9. reset adjust switching threshold vs. junction temperature 4.9 ?40 80 v q , output voltage (v) t j , junction temperature ( c) 5.0 ?20 60 100 40 20 120 v i = 13.5 v i q = 100 a 5.1 160 0 140 500 200 100 0 0 100 v dr , drop voltage (mv) i q , output current (ma) 400 300 50 150 t j = 150 c 6.0 ?40 80 i d , charge current a) t j , junction temperature ( c) 6.8 ?20 60 100 40 20 120 v i = 13.5 v v d = 1 v i q = 100 a 8.0 160 0 140 0 ?40 80 v ud , v ld , switching voltage (v) t j , junction temperature ( c) 1.6 40 120 3.2 160 0 2.8 2.4 2.0 0.4 1.2 0.8 0.9 ?40 80 v radj,th , reset adjust switching threshold (v) t j , junction temperature ( c) 1.3 40 120 160 0 1.5 1.4 1.0 1.2 1.1 v i = 13.5 v i q = 100 a t j = 25 c 12 468 6.4 7.2 7.6 v i = 13.5 v t j = 25 c t j = ?40 c
ncv4299c www. onsemi.com 8 figure 10. sense threshold vs. junction temperature figure 11. output current vs. input voltage figure 12. current consumption vs. junction temperature figure 13. current consumption vs. output current figure 14. r ro , r so resistance vs. junction temperature figure 15. current consumption vs. input voltage ?40 80 v si , sense limit threshold (v) t j , junction temperature ( c) 1.3 40 120 v si,high 160 0 1.5 1.4 1.0 1.2 1.1 1.6 030 i q , output current (ma) v i , input voltage (v) 200 20 4 0 t j = 25 c 10 300 250 50 150 100 400 0 i q , output current (ma) 4.0 80 16 0 40 1.0 3.0 2.0 0 0 120 i q , current consumption (ma) t j , junction temperature ( c) 80 160 40 20 40 30 10 0 120 r ro , r so , resistance (k ) ?40 v i , input voltage (v) 16 20 4 0 10 2 14 4 0 030 i q , current consumption (ma) 12 10 8 6 v si,low i q = 150 ma t j = 125 c v q = 0 v t j , junction temperature ( c) 100 80 60 40 20 0 ?20 ?40 1 10 100 1000 i q , current consumption ( a) 140 120 160 350 v i = 13.5 v i q = 100 a v i = 13.5 v t j = 25 c 1.5 3.5 2.5 0.5 i q = 100 ma i q = 50 ma i q = 25 ma t j = 25 c 15 25 35
ncv4299c www. onsemi.com 9 figure 16. current consumption vs. input voltage figure 17. current consumption vs. input voltage figure 18. output stability vs. output capacitor esr 120 40 618 i q , current consumption a) v i , input voltage (v) 60 81620 14 80 100 12 22 i q = 100 a 24 10 26 3.0 1.0 0.5 0 618 i q , current consumption (ma) v i , input voltage (v) 2.0 81620 14 1.5 2.5 12 22 24 10 26 0.01 75 output capacitor esr ( ) i q , output current (ma) 50 100 25 125 100 150 0 0.1 1 10 unstable region stable region 1 f to 100 f v i = 13.5 v t j = 25 c i q = 100 ma i q = 10 ma i q = 50 ma t j = 25 c t j = 25 c 50 70 90 110
ncv4299c www. onsemi.com 10 typical performance characteristics ? 3.3 v option figure 19. current consumption vs. junction temperature figure 20. current consumption vs. output current t j , junction temperature ( c) i q , output current (ma) 100 80 60 40 20 0 ?20 ?40 1 10 100 1000 140 120 100 80 60 40 20 0 0 2 4 5 figure 21. current consumption vs. input voltage figure 22. output voltage vs. junction temperature v i , input voltage (v) t j , junction temperature ( c) 40 30 20 10 0 0 2 4 12 160 120 80 40 0 ?40 3.20 3.25 3.30 3.35 3.40 figure 23. current consumption vs. input voltage figure 24. output current vs. input voltage v i , input voltage (v) v i , input voltage (v) 26 22 18 14 10 6 0 0.5 1.0 1.5 2.0 2.5 3.0 40 0 0 50 100 150 200 250 300 400 i q , current consumption ( a) 140 120 i q , quiescent current (ma) 160 v q , output voltage (v) i q , current consumption (ma) i q , current consumption (ma) i q , output current (ma) 20 160 v i = 13.5 v i q = 100 a 3 1 v i = 13.5 v t j = 150 c t j = ?40 c t j = 25 c 6 8 10 i q = 25 ma i q = 50 ma i q = 100 ma i q = 150 ma 140 100 60 20 ?20 v i = 13.5 v i q = 100 a 24 20 16 12 8 i q = 50 ma i q = 100 ma i q = 10 ma 10 30 350 t j = 125 c t j = 25 c v q = 0 v t j = 25 c t j = 25 c
ncv4299c www. onsemi.com 11 typical performance characteristics ? 3.3 v option figure 25. output voltage vs. input voltage figure 26. current consumption vs. input voltage v i , input voltage (v) v i , input voltage (v) 12 10 14 8 6 4 2 0 0 1 2 3 4 5 6 24 22 18 16 14 10 8 6 65 70 75 80 85 figure 27. reset trigger threshold vs. junction temperature figure 28. sense threshold vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 140 100 80 60 40 0 ?20 ?40 2.90 2.95 3.00 3.05 3.10 3.15 3.20 160 120 80 40 0 ?40 1.0 1.1 1.2 1.3 1.4 1.5 1.6 figure 29. switching voltage vs. junction temperature figure 30. reset adjust switching threshold vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 160 120 80 40 0 ?40 0 0.4 0.8 1.2 1.6 2.4 2.8 3.2 160 120 80 40 0 ?40 0.9 1.0 1.1 1.2 1.3 1.4 1.5 v q , output voltage (v) i q , current consumption ( a) v rt , reset trigger threshold (v) v si , sense threshold (v) v ud , v ld , switching voltage (v) v radj,th , reset adjust switching threshold (v) v i = 13.5 v t j = 25 c 12 20 26 i q = 100 a 20 120 160 v i = 13.5 v v i = 13.5 v i q = 100 a v si,high v si,low v i = 13.5 v v i = 13.5 v 2.0 t j = 25 c
ncv4299c www. onsemi.com 12 typical performance characteristics ? 3.3 v option figure 31. resistance vs. junction temperature figure 32. charge current vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 160 120 80 40 0 ?40 10 20 30 40 80 40 0 ?40 6.0 6.4 6.8 7.2 7.6 8.0 figure 33. output capacitor esr vs. output current i q , output current (ma) 140 120 100 80 60 40 20 0 0.01 0.1 1 10 100 r ro , r so , resistance (k ) i d , charge current ( a) output capacitor esr ( ) 120 160 v i = 13.5 v v d = 1 v i q = 100 a 160 v i = 13.5 v t j = 25 c unstable region stable region 2.2 f to 100 f
ncv4299c www. onsemi.com 13 application description ncv4299c the ncv4299c is a family of precision micropower voltage regulators with an output current capability of 150 ma at 5.0 v and 3.3 v. the output voltage is accurate within 2% with a maximum dropout voltage of 0.5 v at 100 ma. low quiescent current is a feature drawing only 80 a with a 100 a load. this part is ideal for any and all battery operated microprocessor equipment. microprocessor control logic includes an active reset output ro (with delay), and a si/so monitor which can be used to provide an early warning signal to the microprocessor of a potential impending reset signal. the use of the si/so monitor allows the microprocessor to finish any signal processing before the reset shuts the microprocessor down. internal output resistors on the ro and so pins pulling up to the output pin q reduce external component count. an inhibit function is available on the 14?lead part. with inhibit active, the regulator turns off and the device consumes less that 1.0 a of quiescent current. the active reset circuit operates correctly at an output voltage as low as 1.0 v. the reset function is activated during the powerup sequence or during normal operation if the output voltage drops outside the regulation limits. the reset threshold voltage can be decreased by the connection of an external resistor divider to the radj lead. the regulator is protected against reverse battery, short circuit, and thermal overload conditions. the device can withstand load dump transients making it suitable for use in automotive environments. ncv4299c circuit description the low dropout regulator in the ncv4299c uses a pnp pass transistor to give the lowest possible dropout voltage capability. the current is internally monitored to prevent oversaturation of the device and to limit current during over current conditions. additional circuitry is provided to protect the device during overtemperature operation. the regulator provides an output regulated to 2%. other features of the regulator include an undervoltage reset function and a sense circuit. the reset function has an adjustable time delay and an adjustable threshold level. the sense circuit trip level is adjustable and can be used as an early warning signal to the controller. an inhibit function that turns off the regulator and reduces the current consumption to less than 1.0 a is a feature available in the 14 pin package. output regulator the output is controlled by a precision trimmed reference. the pnp output has saturation control for regulation while the input voltage is low, preventing oversaturation. current limit and voltage monitors complement the regulator design to give safe operating signals to the processor and control circuits. stability considerations the input capacitor c i is necessary for compensating input line reactance. possible oscillations caused by input inductance and input capacitance can be damped by using a resistor of approximately 1.0 in series with c i . the output or compensation capacitor helps determine three main characteristics of a linear regulator: startup delay, load transient response and loop stability. the capacitor value and type should be based on cost, availability, size and temperature constraints. a tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero esr can cause instability. the aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (?25 c to ?40 c), both the value and esr of the capacitor will vary considerably. the capacitor manufacturer?s data sheet usually provides this information. the value for the output capacitor c q shown in figure 34 should work for most applications, however, it is not necessarily the optimized solution. stability is guaranteed at values c q 22 f and an esr 4 within the operating temperature range. actual limits are shown in a graph in the typical performance characteristics section.
ncv4299c www. onsemi.com 14 ncv4299c i d so q si ro gnd v bat figure 34. test and application circuit showing all compensation and sense elements 0.1 f c i * c d r radj1 r radj2 r s11 r s12 c q ** 22 f v dd microprocessor i/o i/o *c i required if regulator is located far from the power supply filter. **c q required for stability. cap must operate at minimum temperature expected. ***this rc filter is only required when transients with slew rate in excess of 10 v/ s may be present on the inh voltage source during operation. the filter is not required when inh is connected to a noise?free dc voltage. radj inh inh c inh *** 0.01 f r inh *** 51k ncv4299c i d so q si ro gnd v bat figure 35. test and application circuit showing all compensation and sense elements for 8 pin package part 0.1 f c i * c d r radj1 r radj2 r s11 r s12 c q ** 22 f v dd microprocessor i/o i/o *c i required if regulator is located far from the power supply filter. **c q required for stability. cap must operate at minimum temperature expected. radj
ncv4299c www. onsemi.com 15 reset output (ro) a reset signal, reset output (ro, low voltage) is generated as the ic powers up. after the output voltage v q increases above the reset threshold voltage v rt , the delay timer d is started. when the voltage on the delay timer v d passes v ud , the reset signal ro goes high. d pin voltage in steady state is typically 2.5 v. a discharge of the delay timer (v d ) is started when v q drops and stays below the reset threshold voltage v rt . when the voltage of the delay timer (v d ) drops below the lower threshold voltage v ld , the reset output voltage v ro is brought low to reset the processor. the reset output ro is an open collector npn transistor, controlled by a low voltage detection circuit. the circuit is functionally independent of the rest of the ic, thereby guaranteeing that ro is valid for v q as low as 1.0 v. figure 36. reset timing diagram v i v q v d v ld v rt v ro,sat v ro t t < t rr dv dt i d c d v ud t power?on?reset thermal shutdown voltage dip at input undervoltage secondary spike overload at output t t rr t d reset adjust (radj) the reset threshold v rt can be decreased from a typical value of 4.67 v to as low as 3.5 v by using an external voltage divider connected from the q lead to the pin radj, as shown in figure 34. the resistor divider keeps the voltage above the v radj,th , (typ. 1.36 v), for the desired input voltages and overrides the internal threshold detector. adjust the voltage divider according to the following relationship: v thres v radj, th (r adj1 r adj2 ) r adj2 (eq. 1) if the reset adjust option is not needed, the radj?pin should be connected to gnd causing the reset threshold to go to its default value (typ. 4.67 v). reset delay (d) the reset delay circuit provides a delay (programmable by capacitor c d ) on the reset output ro lead. the delay lead d provides charge current i d (typically 7.1 a) to the external delay capacitor c d during the following times: 1. during powerup (once the regulation threshold has been exceeded). 2. after a reset event has occurred and the device is back in regulation. the delay capacitor is set to discharge when the regulation (v rt , reset threshold voltage) has been violated. when the delay capacitor discharges to down to v ld , the reset signal ro pulls low.
ncv4299c www. onsemi.com 16 setting the delay time the delay time is set by the delay capacitor c d and the charge current i d . the time is measured by the delay capacitor voltage charging from the low level of v d,sat to the higher level v ud . the time delay follows the equation: t d [c d (v ud ?v d, sat )] i d (eq. 2) example: using c d = 100 nf. use the typical value for v d,sat = 0.1 v. use the typical value for v ud = 1.85 v. use the typical value for delay charge current i d = 7.1 a. t d [100 nf(1.85?0.1 v)] 7.1 a 24.6 ms (eq. 3) when the output voltage v q drops below the reset threshold voltage v rt , the voltage on the delay capacitor v d starts to drop. the time it takes to drop below the lower threshold voltage of v ld is the reset reaction time, t rr . this time is typically 1.6 s for a delay capacitor of 0.1 f. the reset reaction time can be estimated from the following relationship: t rr 16 ns nf c d (eq. 4) sense input (si)/sense output (so) voltage monitor an on?chip comparator is available to provide early warning to the microprocessor of a possible reset signal. the reset signal typically turns the microprocessor off instantaneously. this can cause unpredictable results with the microprocessor. the signal received from the so pin will allow the microprocessor time to complete its present task before shutting down. this function is performed by a comparator referenced to the band gap voltage. the actual trip point can be programmed externally using a resistor divider to the input monitor (si) (figure 34). the typical threshold is 1.36 v on the si pin. signal output figure 37 shows the so monitor waveforms as a result of the circuits depicted in figure 34. as the output voltage v q falls, the monitor threshold v si,low is crossed. this causes the voltage on the so output to go low sending a warning signal to the microprocessor that a reset signal may occur in a short period of time. t wa r n i n g is the time the microprocessor has to complete the function it is currently working on and get ready for the reset shutdown signal. when the voltage on the so goes low and the ro stays high the current consumption is typically 400 a. v q v si v si,low v ro v so t warning figure 37. so warning timing waveform t psolh t psohl t t sense input voltage v si,high v si,low sense output high low figure 38. sense timing diagram calculating power dissipation in a single output linear regulator the maximum power dissipation for a single output regulator is: p d(max) [v i(max) ?v q(min) ]i q(max) v i(max) iq (eq. 5) where: v i(max) is the maximum input voltage, v q(min) is the minimum output voltage, i q(max) is the maximum output current for the application, and i q is the quiescent current the regulator consumes at i q(max) . once the value of p d(max) is known, the maximum permissible value of r ja can be calculated: r ja (150 c?t a ) p d (eq. 6)
ncv4299c www. onsemi.com 17 the value of r ja can then be compared with those in the package section of the data sheet. those packages with r ja ?s less than the calculated value in equation 6 will keep the die temperature below 150 c. in some cases, none of the packages will be sufficient to dissipate the heat generated by the ic, and an external heatsink will be required. thermal resistance r ja vs. copper area is shown in figure 39. 0 50 100 150 250 0 100 200 300 400 500 600 700 copper heat spreader area (mm 2 ) thermal resistance, junction? to?ambient, r ja , ( c/w) figure 39. thermal resistance r ja vs. copper area 200 1 oz so?14 2 oz so?14 1 oz so?8 2 oz so?8 heatsinks a heatsink effectively increases the surface area of the package to improve the flow of heat away from the ic and into the surrounding air. each material in the heat flow path between the ic and the outside environment will have a thermal resistance. like series electrical resistances, these resistances are summed to determine the value of r ja : r ja r jc r cs r sa (eq. 7) where: r jc = the junction?to?case thermal resistance, r cs = the case?to?heatsink thermal resistance, and r sa = the heatsink?to?ambient thermal resistance. r jc appears in the package section of the data sheet. like r ja , it too is a function of package type. r cs and r sa are functions of the package type, heatsink and the interface between them. these values appear in heatsink data sheets of heatsink manufacturers. thermal, mounting, and heatsinking are discussed in the on semiconductor application note an1040/d, available on the on semiconductor website. ordering information device package shipping ? NCV4299CD133R2G so?8 (pb?free) 2500 / tape & reel ncv4299cd150r2g so?8 (pb?free) 2500 / tape & reel ncv4299cd233r2g so?14 (pb?free) 2500 / tape & reel ncv4299cd250r2g so?14 (pb?free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncv4299c www. onsemi.com 18 package dimensions soic?8 nb case 751?07 issue ak seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751?01 thru 751?06 are obsolete. new standard is 751?07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?x? ?y? g m y m 0.25 (0.010) ?z? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
ncv4299c www. onsemi.com 19 package dimensions soic?14 nb case 751a?03 issue k notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b does not include dambar protrusion. allowable protrusion shall be 0.13 total in excess of at maximum material condition. 4. dimensions d and e do not include mold protrusions. 5. maximum mold protrusion 0.15 per side. h 14 8 7 1 m 0.25 b m c h x 45 seating plane a1 a m s a m 0.25 b s c b 13x b a e d e detail a l a3 detail a dim min max min max inches millimeters d 8.55 8.75 0.337 0.344 e 3.80 4.00 0.150 0.157 a 1.35 1.75 0.054 0.068 b 0.35 0.49 0.014 0.019 l 0.40 1.25 0.016 0.049 e 1.27 bsc 0.050 bsc a3 0.19 0.25 0.008 0.010 a1 0.10 0.25 0.004 0.010 m 0 7 0 7 h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.019 6.50 14x 0.58 14x 1.18 1.27 dimensions: millimeters 1 pitch soldering footprint* *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncv4299c/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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